Digital signal processing is the basis for many technology areas. These areas include, for example, digital communication, audio, multimedia, and video. Using digital signal processing, analog data is converted into digital data. The analog data may be sampled at discrete intervals generated by a sampling clock that are carefully chosen to ensure an accurate representation of an original analog signal. The sampling clock may have inaccuracy in its frequency which results in a drifting timing offset across samples from an ideal sample interval.
This inaccuracy in the sampling clock, however, may require digital timing correction to correct the drifting timing offsets between the samples to recover the accurate representation of the analog signal. Sometimes, an oversampled clock may be employed to generate higher quality results in the digital sampling correction. Interpolation between neighboring samples may be used to attempt correction of the drifting timing offsets. A base sample used for the interpolation may have to be shifted accordingly so the interpolation is performed between the samples. Conventionally, this logic has been implemented using, for example, a buffer and the address generation logic for the neighboring samples for the interpolation. If a base sample is shifted, a read pointer in the buffer is shifted accordingly to permit selection of a correct sample for the interpolation.
Depending on sampling frequency offset present in the samples and the length of a packet received, a significant number of shifts may be required. A buffer designed to accommodate the number of shifts may result in significant memory requirements, depending on the timing offset and the packer size. For continuous transmission operations, such requirements may not be feasible as this could necessitate significant memory requirements.
Other features of the present embodiments will be apparent from the accompanying drawings and from the detailed description that follows.